Lattice Prompt 1.1 Brings AI Assistance to FPGA Design and Timing Closure

FPGA design still demands a long chain of work after the RTL is written: synthesis, placement, routing, timing analysis, simulation and bitstream generation. Lattice Prompt 1.1 aims to shorten that chain by letting engineers describe design tasks in natural language and use an AI assistant to operate Lattice’s development tools. The company says some tasks can see productivity gains of 10 times or more; three examples show what that claim means in practice.

The idea fits a broader shift toward AI tools that handle concrete workshop tasks. One example is an electric screwdriver that uses a camera to identify a screw and recommend the matching bit. Its connected case displays a close-up of the screw and lights the LED beside the correct bit. The screwdriver also offers Auto Torque Assist, which matches applied torque to the identified screw, while still allowing manual operation. The FPGA application is more complex, but follows a similar pattern: the user describes an objective, and software helps select and run the relevant operations.

AI assistance around existing FPGA tools

Lattice introduced Prompt as a way to connect an AI agent with its FPGA development environment. It doesn’t include its own large language model. Instead, it is designed to work with compatible assistants such as Claude Code and Cursor, along with the models those tools support. That lets engineering teams keep their existing AI workflow while adding Lattice-specific design knowledge and tool access.

The connection uses the Model Context Protocol (MCP), an open standard for connecting AI applications to external tools, alongside Skills that supply instructions and specialized knowledge. Through these mechanisms, the agent can access Lattice device information, IP catalogs, reference designs and development tools. Deterministic validators check results against design rules and constraints. The division of work matters: the AI agent reasons about the request and proposes actions; Prompt supplies FPGA-specific context and a way to carry those actions out.

Prompt 1.0, released in September 2026, focused on automating tasks in Lattice Radiant, including synthesis, placement, routing, timing analysis, simulation and bitstream generation. Version 1.1, released on 30 October 2026, adds design-consultant functions for building systems with Lattice Propel, developing RISC-V firmware, closing timing, running RTL simulations and debugging hardware with Lattice Reveal.

Propel matters because many FPGA systems include embedded processors. Lattice offers four customizable RISC-V soft-core variants: Nano for basic control and monitoring; SM for small bare-metal systems; MC for more capable microcontroller applications; and RX for higher-performance use, including systems that need a real-time operating system. Prompt 1.1 can help assemble processor-based systems, configure IP blocks and peripherals, and write related firmware, including drivers and linker scripts.

Under the interface, two MCP servers divide the work. The Lattice Prompt Server provides design knowledge, validation and execution, including Propel integration. The Lattice Radiant MCP Server handles the Radiant implementation flow, including timing analysis and closure. The AI agent selects the relevant server for a task, while the designer continues using a preferred assistant.

Lattice says design files, build logs and license settings stay on the user’s machine when using Prompt. That describes Prompt’s handling of those items; users still need to consider how their chosen AI assistant handles data.

Three engineering examples

The first example applies Prompt to industrial motion control. Motors, sensors and actuators in such systems need predictable communication. Lattice’s demonstration starts with a request for a low-power, deterministic Time-Sensitive Networking (TSN) Ethernet endpoint for a motion-control drive. TSN refers to Ethernet enhancements intended to support deterministic communication. Prompt can help identify suitable device information and IP, run development tools, and work toward an implementation with an FPGA bitstream, timing and simulation results, and documentation.

The second example tackles a code-porting task. Lattice engineers began with optical coherence tomography (OCT) reconstruction code written in NVIDIA’s CUDA environment and set out to run it on a Lattice Avant FPGA. OCT uses reflected light to form cross-sectional images of materials and biological tissue. The team asked Prompt to port the code. The workflow produced a Python implementation checked against the CUDA version, then RTL checked against the Python implementation, before implementing the design on the FPGA.

The resulting design ran at 200 MHz. Lattice reports that the engineers had no previous experience with CUDA or OCT, and that the full process took about 30 hours. The company estimates that conventional development would have taken months. The staged checks are a significant part of the example: the generated RTL was compared against an intermediate Python model, rather than treated as correct simply because it compiled.

The third example focuses on timing closure, a familiar source of repeated implementation work. A Relay-BP decoder associated with quantum error correction was targeting 200 MHz on a Lattice Avant FPGA but initially reached only about 98 MHz. The request was to fix the timing problem, described as missing the 200 MHz target by 5 ns. Prompt helped identify timing violations and guide implementation changes, reducing the number of iterations.

Lattice reports that the design then met 200 MHz with 0.075 ns of positive slack at 85°C, zero hold-time errors and passing simulations. The work took four hours; the company estimates that conventional methods would take days. Those results are specific to this design and reported workflow, but they point to where AI assistance may be most useful: navigating tool operations and timing reports while an engineer evaluates the proposed changes.

What to watch

Lattice Prompt 1.1 is available as a free download with a one-command installer and user guide. The examples span system construction, code translation and timing closure, but they are company demonstrations rather than independent comparisons across projects. The practical test for design teams will be whether the generated work remains easy to inspect and verify in their own devices, constraints and tool flows.

AI assistance in electronic design is still developing, particularly around independent verification and hardware debugging. A useful next step would be workflows in which separate tools or agents generate, check and test designs, with engineers able to trace each result. For now, Prompt’s strongest case is reducing the effort involved in getting from a clear design request to a tool-driven implementation that can still be checked against engineering constraints.